1. Field of the Invention
The present invention relates to a microprocessor including an instruction decoder for decoding instructions to be executed, and more particularly to a microprocessor compatible with software represented by different types of instruction formats.
In conformity with the rapid progress of LSI techniques, the efficiency of microprocessors (or microcomputers) has remarkably improved. Recently, microprocessors with high performance have been offered at low cost. Further, in response to urgent requirements, new types of microprocessors implementing architectures designed on the basis of the latest LSI technology have been developed and have been widely used in many industrial fields. Therefore, development of software for a newly designed microprocessor is often required in a short period of time.
On the other hand, considering the hardware architecture of a microprocessor, 16-bit or 32-bit parallel processing types of microprocessors have been developed. A large amount of software developed for 8-bit parallel processing type of microprocessors cannot be directly adapted to the 16-bit or 32-bit parallel processing type microprocessor (hereinafter, referred to as 16-bit or 32-bit microprocessor). Therefore, new software or modified software is required for the 16-bit or 32-bit microprocessor. It is, however, impossible to quickly develop new software or modify the existing software, because of necessities of a long period a complex handwork and a high cost.
To avoid this problem, an 8-bit microprocessor has been incorporated into a conventional 16-bit microprocessor system so that both the 16-bit microprocessor and the 8-bit microprocessor are independently installed and employed in the system. In the operation of this system, when the software for the 16-bit microprocessor is to be executed, the 8-bit microprocessor is decoupled from a data bus add an address bus to which a memory is coupled. On the other hand, when the 8-bit microprocessor is to be used, the 16-bit processor is decoupled from the system data bus and the system address bus. This decoupling operation is performed by an interface device inserted between the system buses and the 8-bit and 16-bit microprocessors.
According to this system, two microprocessors are independently required. In other words, two control processing units and two instruction decoders are required. Further, the interface device for controlling the bus connection is required. Therefore, the system has a disadvantage that its size becomes very large. Furthermore, the system cost is increased due to the many hardware elements. Moreover, in the system operation, the instruction decoder and the control processing unit (CPU) of the 8-bit microprocessor cannot be used when an instruction of the 16-bit microprocessor is executed, and vice versa.